Traditional bipolar circuitry design relies on high performance vertical transistors for many dynamic functions. Complementary bipolar circuits offer the benefits of reduced power dissipation, increased switching speed, and more flexible circuit design in comparison to designs with resistive or active loads. Benefits obtainable by fabricating complementary bipolar circuits in silicon-on-sapphire (SOS) include: latch up immunity, high packing density, radiation immunity and faster circuits. Previous work in the area of bipolar junction transistors in SOS includes the fabrication of epitaxial vertical bipolar junction transistors in SOS, lateral bipolar junction transistors in SOS, ion implanted vertical bipolar junction transistors in SOS, and bipolar junction transistors integrated with CMOS transistors in SOS. The processing for manufacturing these types of transistors, all of which have a single polarity, is not generally modifiable to manufacturing complementary transistors.
Almost all present complementary bipolar transistor manufacturing techniques use some form of junction isolation method. However, transistors manufactured by the junction isolation method have undesirable performance limitations such as parasitic capacitance and latch-up susceptibility.
A process for manufacturing complementary bipolar devices is described in Feindt, S., et al., "A Complementary Bipolar Process On Bonded Wafers," Proceedings of the Second International Symposium On Semiconductor Wafer Bonding: Science, Technology, And Applications, Proceedings Volume 93-29, pages 189-196, The Electrochemical Society, Inc. (1993). The structure manufactured by the process described in this paper uses a buried silicon dioxide, or oxide layer to provide dielectric isolation between PNP and NPN devices. One limitation of such use of a buried oxide layer is the relatively low thermal conductivity of silicon dioxide. The buried oxide layer does not conduct heat away from the PNP and NPN devices very well, thereby limiting the current carrying capacity of such devices.
Sapphire has excellent dielectric properties, as well has high thermal conductivity (42 W/m.multidot.K), compared to the thermal conductivity of silicon dioxide (1 W/m.multidot.K). A junction device having a sapphire substrate should having a higher current carrying capacity than a junction device fabricated on a silicon dioxide substrate. The excellent electrical insulating properties of sapphire would provide devices having reduced parasitic capacitance, and in which dynamic power consumption is minimized. Therefore, a need exists for a method for manufacturing complementary, vertical bipolar transistors using sapphire to take advantage of its dielectric and thermal characteristics. Structures manufactured with sapphire should exhibit higher current carrying capacity than structures using buried oxide as an insulator. Complementary bipolar transistors embodying sapphire as an insulator would rival CMOS circuitry in processing speed and chip size.